static void apic_pm_activate(void);
-int modern_apic(void)
+static int modern_apic(void)
{
unsigned int lvr, version;
/* AMD systems use old APIC versions, so check the CPU */
#define APIC_DIVISOR 1
-void __setup_APIC_LVTT(unsigned int clocks)
+static void __setup_APIC_LVTT(unsigned int clocks)
{
unsigned int lvtt_value, tmp_value, ver;
* APIC irq that way.
*/
-int __init calibrate_APIC_clock(void)
+static int __init calibrate_APIC_clock(void)
{
unsigned long long t1 = 0, t2 = 0;
long tt1, tt2;
return result;
}
-u32 get_apic_bus_cycle(void)
-{
- return bus_cycle;
-}
-
static unsigned int calibration_result;
void __init setup_boot_APIC_clock(void)
c->x86_cache_alignment = 128;
}
-/*
- * Early probe support logic for ppro memory erratum #50
- *
- * This is called before we do cpu ident work
- */
-
-int __devinit ppro_with_ram_bug(void)
-{
- /* Uses data from early_cpu_detect now */
- if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
- boot_cpu_data.x86 == 6 &&
- boot_cpu_data.x86_model == 1 &&
- boot_cpu_data.x86_mask < 8) {
- printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
- return 1;
- }
- return 0;
-}
-
-
/*
* P4 Xeon errata 037 workaround.
* Hardware prefetcher may cause stale data to be loaded into the cache.
* Collects information of correctable errors and notifies
* Dom0 via an event.
*/
-void mce_amd_checkregs(void *info)
+static void mce_amd_checkregs(void *info)
{
mctelem_cookie_t mctc;
struct mca_summary bs;
return 0;
}
-void intel_UCR_handler(struct mcinfo_bank *bank,
+static void intel_UCR_handler(struct mcinfo_bank *bank,
struct mcinfo_global *global,
struct mcinfo_extended *extension,
struct mca_handle_result *result)
static int x2apic_phys = 0; /* By default we use logical cluster mode. */
boolean_param("x2apic_phys", x2apic_phys);
-__init int probe_x2apic_phys(void)
+static int __init probe_x2apic_phys(void)
{
return x2apic && x2apic_phys && x2apic_is_available() &&
iommu_supports_eim();
}
-__init int probe_x2apic_cluster(void)
+static int __init probe_x2apic_cluster(void)
{
return x2apic && !x2apic_phys && x2apic_is_available() &&
iommu_supports_eim();
s->gate = val;
}
-int pit_get_gate(PITState *pit, int channel)
+static int pit_get_gate(PITState *pit, int channel)
{
ASSERT(spin_is_locked(&pit->lock));
return pit->hw.channels[channel].gate;
vcpu_end_shutdown_deferral(curr);
}
-void dpci_ioport_read(uint32_t mport, ioreq_t *p)
+static void dpci_ioport_read(uint32_t mport, ioreq_t *p)
{
int i, sign = p->df ? -1 : 1;
uint32_t data = 0;
}
}
-void dpci_ioport_write(uint32_t mport, ioreq_t *p)
+static void dpci_ioport_write(uint32_t mport, ioreq_t *p)
{
int i, sign = p->df ? -1 : 1;
uint32_t data;
return vlapic_find_highest_vector(&vlapic->regs->data[APIC_ISR]);
}
-uint32_t vlapic_get_ppr(struct vlapic *vlapic)
+static uint32_t vlapic_get_ppr(struct vlapic *vlapic)
{
uint32_t tpr, isrv, ppr;
int isr;
return X86EMUL_OKAY;
}
-void vlapic_pt_cb(struct vcpu *v, void *data)
+static void vlapic_pt_cb(struct vcpu *v, void *data)
{
*(s_time_t *)data = hvm_get_guest_time(v);
}
{
}
-void /*__init*/ __print_IO_APIC(void)
+static void /*__init*/ __print_IO_APIC(void)
{
int apic, i;
union IO_APIC_reg_00 reg_00;
unsigned apic_gsi_base(int apic);
-int apic_pin_2_gsi_irq(int apic, int pin)
+static int apic_pin_2_gsi_irq(int apic, int pin)
{
int idx, irq;
io_emul_stub[9] = 0xc3;
}
-int __init proliant_quirk(struct dmi_system_id *d)
+static int __init proliant_quirk(struct dmi_system_id *d)
{
ioemul_handle_quirk = ioemul_handle_proliant_quirk;
return 0;
{ }
};
-int __init ioport_quirks_init(void)
+static int __init ioport_quirks_init(void)
{
dmi_check_system(ioport_quirks_tbl);
return 0;
return irq;
}
-void dynamic_irq_cleanup(unsigned int irq)
+static void dynamic_irq_cleanup(unsigned int irq)
{
struct irq_desc *desc = irq_to_desc(irq);
unsigned long flags;
#include <xen/paging.h>
#include <xen/config.h>
#include <xen/sched.h>
+#include "private.h" /* for hap_gva_to_gfn_* */
#define _hap_gva_to_gfn(levels) hap_gva_to_gfn_##levels##level
#define hap_gva_to_gfn(levels) _hap_gva_to_gfn(levels)
/* HAP VRAM TRACKING SUPPORT */
/************************************************/
-int hap_enable_vram_tracking(struct domain *d)
+static int hap_enable_vram_tracking(struct domain *d)
{
int i;
struct sh_dirty_vram *dirty_vram = d->arch.hvm_domain.dirty_vram;
return 0;
}
-int hap_disable_vram_tracking(struct domain *d)
+static int hap_disable_vram_tracking(struct domain *d)
{
int i;
struct sh_dirty_vram *dirty_vram = d->arch.hvm_domain.dirty_vram;
return 0;
}
-void hap_clean_vram_tracking(struct domain *d)
+static void hap_clean_vram_tracking(struct domain *d)
{
int i;
struct sh_dirty_vram *dirty_vram = d->arch.hvm_domain.dirty_vram;
flush_tlb_mask(&d->domain_dirty_cpumask);
}
-void hap_vram_tracking_init(struct domain *d)
+static void hap_vram_tracking_init(struct domain *d)
{
paging_log_dirty_init(d, hap_enable_vram_tracking,
hap_disable_vram_tracking,
/************************************************/
/* hap code to call when log_dirty is enable. return 0 if no problem found. */
-int hap_enable_log_dirty(struct domain *d)
+static int hap_enable_log_dirty(struct domain *d)
{
/* turn on PG_log_dirty bit in paging mode */
hap_lock(d);
return 0;
}
-int hap_disable_log_dirty(struct domain *d)
+static int hap_disable_log_dirty(struct domain *d)
{
hap_lock(d);
d->arch.paging.mode &= ~PG_log_dirty;
return 0;
}
-void hap_clean_dirty_bitmap(struct domain *d)
+static void hap_clean_dirty_bitmap(struct domain *d)
{
/* set l1e entries of P2M table to be read-only. */
p2m_change_entry_type_global(d, p2m_ram_rw, p2m_ram_logdirty);
return pg;
}
-void hap_free_p2m_page(struct domain *d, struct page_info *pg)
+static void hap_free_p2m_page(struct domain *d, struct page_info *pg)
{
hap_lock(d);
ASSERT(page_get_owner(pg) == d);
int set_p2m_entry(struct domain *d, unsigned long gfn, mfn_t mfn,
unsigned int page_order, p2m_type_t p2mt);
-int
+static int
p2m_pod_cache_add(struct domain *d,
struct page_info *page,
unsigned long order)
}
/* This function fress log dirty bitmap resources. */
-void paging_log_dirty_teardown(struct domain*d)
+static void paging_log_dirty_teardown(struct domain*d)
{
log_dirty_lock(d);
paging_free_log_dirty_bitmap(d);
#include <asm/x86_emulate.h>
#include <asm/traps.h>
#include <asm/hvm/vpt.h>
+#include <asm/hypercall.h>
#include <public/arch-x86/cpuid.h>
/*
vcpu_unpause(v);
}
-char *trapstr(int trapnr)
+static char *trapstr(int trapnr)
{
static char *strings[] = {
"divide error", "debug", "nmi", "bkpt", "overflow", "bounds",
send_guest_trap(d, 0, TRAP_nmi);
}
-asmlinkage void mem_parity_error(struct cpu_user_regs *regs)
+static void mem_parity_error(struct cpu_user_regs *regs)
{
switch ( opt_nmi[0] )
{
outb((inb(0x61) & 0x0b) | 0x00, 0x61); /* enable parity check */
}
-asmlinkage void io_check_error(struct cpu_user_regs *regs)
+static void io_check_error(struct cpu_user_regs *regs)
{
switch ( opt_nmi[0] )
{
}
#define decode_segment_failed x86_seg_tr
-enum x86_segment
-decode_segment(
- uint8_t modrm_reg)
+static enum x86_segment
+decode_segment(uint8_t modrm_reg)
{
switch ( modrm_reg )
{
list_del_init(&svc->runq_elem);
}
-void burn_credits(struct csched_vcpu *svc, s_time_t now)
+static void burn_credits(struct csched_vcpu *svc, s_time_t now)
{
s_time_t delta;
/* ----------------------------------------------------------------------- */
-uint64_t xvhash(unsigned char m[],
- unsigned int mbytes,
- uint64_t *tagl,
- vmac_ctx_t *ctx)
-{
- uint64_t ch, cl, rh, rl, *mptr;
- #if (VMAC_TAG_LEN == 128)
- uint64_t ch2, cl2, rh2, rl2;
- #endif
- const uint64_t *kptr = (uint64_t *)ctx->nhkey;
- int i, remaining;
-
- remaining = mbytes % VMAC_NHBYTES;
- i = mbytes-remaining;
- mptr = (uint64_t *)(m+i);
- if (i) vhash_update(m,i,ctx);
-
- ch = ctx->polytmp[0];
- cl = ctx->polytmp[1];
- #if (VMAC_TAG_LEN == 128)
- ch2 = ctx->polytmp[2];
- cl2 = ctx->polytmp[3];
- #endif
-
- if (remaining) {
- #if (VMAC_TAG_LEN == 128)
- nh_16_2(mptr,kptr,2*((remaining+15)/16),rh,rl,rh2,rl2);
- rh2 &= m62;
- #else
- nh_16(mptr,kptr,2*((remaining+15)/16),rh,rl);
- #endif
- rh &= m62;
- if (i) {
- poly_step(ch,cl,ctx->polykey[0],ctx->polykey[1],rh,rl);
- #if (VMAC_TAG_LEN == 128)
- poly_step(ch2,cl2,ctx->polykey[2],ctx->polykey[3],rh2,rl2);
- #endif
- } else {
- ADD128(ch,cl,rh,rl);
- #if (VMAC_TAG_LEN == 128)
- ADD128(ch2,cl2,rh2,rl2);
- #endif
- }
- }
-
- #if VMAC_USE_SSE2
- _mm_empty(); /* SSE2 version of poly_step uses mmx instructions */
- #endif
- vhash_abort(ctx);
- remaining *= 8;
-#if (VMAC_TAG_LEN == 128)
- *tagl = l3hash(ch2, cl2, ctx->l3key[2], ctx->l3key[3],remaining);
-#endif
- return l3hash(ch, cl, ctx->l3key[0], ctx->l3key[1],remaining);
-}
-
uint64_t vhash(unsigned char m[],
unsigned int mbytes,
uint64_t *tagl,
atomic_dec(&print_everything);
}
-void console_putc(char c)
-{
- serial_putc(sercon_handle, c);
-}
-
-int console_getc(void)
-{
- return serial_getc(sercon_handle);
-}
-
/*
* printk rate limiting, lifted from Linux.
*
return 0;
}
-int __init get_iommu_capabilities(u8 bus, u8 dev, u8 func, u8 cap_ptr,
+static int __init get_iommu_capabilities(u8 bus, u8 dev, u8 func, u8 cap_ptr,
struct amd_iommu *iommu)
{
u32 cap_header, cap_range, misc_info;
return irq;
}
-void enable_iommu(struct amd_iommu *iommu)
+static void enable_iommu(struct amd_iommu *iommu)
{
unsigned long flags;
return (allocate_iommu_table_struct(&iommu->event_log, "Event Log"));
}
-int __init amd_iommu_init_one(struct amd_iommu *iommu)
+static int __init amd_iommu_init_one(struct amd_iommu *iommu)
{
if ( allocate_cmd_buffer(iommu) != 0 )
goto error_out;
send_iommu_command(iommu, cmd);
}
-int amd_iommu_is_dte_page_translation_valid(u32 *entry)
-{
- return (get_field_from_reg_u32(entry[0],
- IOMMU_DEV_TABLE_VALID_MASK,
- IOMMU_DEV_TABLE_VALID_SHIFT) &&
- get_field_from_reg_u32(entry[0],
- IOMMU_DEV_TABLE_TRANSLATION_VALID_MASK,
- IOMMU_DEV_TABLE_TRANSLATION_VALID_SHIFT));
-}
-
static u64 iommu_l2e_from_pfn(struct page_info *table, int level,
unsigned long io_pfn)
{
return 0;
}
-u16 apicid_to_bdf(int apic_id)
+static u16 apicid_to_bdf(int apic_id)
{
struct acpi_drhd_unit *drhd = ioapic_to_drhd(apic_id);
struct acpi_ioapic_unit *acpi_ioapic_unit;
flush_non_present_entry, flush_dev_iotlb);
}
-void iommu_flush_all(void)
+static void iommu_flush_all(void)
{
struct acpi_drhd_unit *drhd;
struct iommu *iommu;
iommu_domid_release(d);
}
-int intel_iommu_map_page(
+static int intel_iommu_map_page(
struct domain *d, unsigned long gfn, unsigned long mfn)
{
struct hvm_iommu *hd = domain_hvm_iommu(d);
return 0;
}
-int intel_iommu_unmap_page(struct domain *d, unsigned long gfn)
+static int intel_iommu_unmap_page(struct domain *d, unsigned long gfn)
{
struct acpi_drhd_unit *drhd;
struct iommu *iommu;
return 0;
}
-int intel_iommu_assign_device(struct domain *d, u8 bus, u8 devfn)
+static int intel_iommu_assign_device(struct domain *d, u8 bus, u8 devfn)
{
struct acpi_rmrr_unit *rmrr;
int ret = 0, i;
}
static u32 iommu_state[MAX_IOMMUS][MAX_IOMMU_REGS];
-void vtd_suspend(void)
+static void vtd_suspend(void)
{
struct acpi_drhd_unit *drhd;
struct iommu *iommu;
}
}
-void vtd_resume(void)
+static void vtd_resume(void)
{
struct acpi_drhd_unit *drhd;
struct iommu *iommu;
return ret;
}
-int __iommu_flush_iec(struct iommu *iommu, u8 granu, u8 im, u16 iidx)
+static int __iommu_flush_iec(struct iommu *iommu, u8 granu, u8 im, u16 iidx)
{
int ret;
ret = queue_invalidate_iec(iommu, granu, im, iidx);
__u32 hi_address;
} __attribute__ ((packed));
+void msi_compose_msg(struct pci_dev *pdev, int irq,
+ struct msi_msg *msg);
#endif /* __ASM_MSI_H */
#endif
struct domain;
+int is_passive(struct domain *d);
void free_xenoprof_pages(struct domain *d);
int do_xenoprof_op(int op, XEN_GUEST_HANDLE(void) arg);